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Northab is looking for ASIC Synthesis & STA Engineer for one of its customers in Lund.

Assignment description

Our Client is investing heavily in the future 5G technology where leading-edge ASIC and FPGA development is key. They are significantly strengthening the capacity in the development of state-of-the-art digital ASIC and FPGA with a great number of talented engineers to meet this challenge.

Since 2014, Lund has been a competence center for radio network development: activities span from HW and SW product development to research and standardization.

They are looking for Experienced, Creative, and Innovative engineers to join their world class team. You will have a unique opportunity to work and gain competence in several areas such as synthesis, RTL-design, STA, integration, & timing/area/power closure. The organization works in accordance to the Lean and Agile principles with close team interaction.

Main competences:

ASIC Backend



Formality (equivalence check)

Low Power / UPF

Meritorious if you've been working with 7 nm or 10 nm technology.

You need to be self-driven, but with team spirit. Leaderships quality is meritorious.

Responsibilities & Tasks:

- SoC level STA

- Timing constraints development

- Timing sign off

- Netlist generation & Synthesis

- Floorplan development

- Acting as main interface towards physical implementation team

- Continuously improve and optimize ways of working.

- Participate in daily and periodic agile meetings

Key Qualifications:

- BSc or MSc level in Electrical Engineering, Computer Science, or equivalent education.

- At least 5 years of relevant work experience.

- Good understanding of VHDL or System Verilog.

- Significant experience of EDA tools for Synthesis & Timing/Area/Power closure

- Significant experience from Static Timing Analysis and timing sign off

- Experience in DFT (Design For Test)

- Knowledge in scripting languages (Python, Perl, TCL, Linux Shell scripting etc.)

- Experience from UNIX/Linux

- Communication and presentation skills in English are essential.

- Quality-consciousness.

- Travels may be needed but not required on a frequent basis.

Following experience will be a beneficial asset:

- Multi/Many Core CPU Architecture Knowledge a plus

- Experience from source code repositories such as Clear Case and Git

- Experience with Synopsis Spyglass, Primetime, Design Compiler & Formality

- Knowledge about mobile communication standards is an advantage.

- Knowledge of floor planning and physical implementation is an advantage

Personal qualifications:

You have a great interest in learning new things every day and want to make a difference. You have a very positive attitude and thrive on new challenges. You are keen to solve problems and do so creatively. Where there is change you see opportunities. You are a strong team player and a very communicative person but you also work well independently. You make sure to reach results with high quality and on time.

Location - Lund

Start Date - 01 Mar 2021

End Date - 30 Jun 2021

Detta är en jobbannons med titeln "ASIC Synthesis & STA Engineer" hos företaget Northab AB och publicerades på workey.se den 7 januari 2021 klockan 23:16.

Hur du söker jobbet

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